Silicon Validation Lead, Google Cloud, TPU
Bengaluru · On-site (inferred from location)
- SystemVerilog
- UVM
- Functional Coverage
- SVA
- +2
Not disclosed
Added by ChipJobs from Google India's careers page · Posted · 1 day ago · Checked
Google India
Fabless · 5000+ people · Bengaluru · www.google.com
Publishes a salary range on 0 of 38 live roles.
India has no pay-transparency law, so almost no employer publishes a band on an Indian posting. We track this figure for every employer on the board rather than filling the gap with an estimate of our own.
Live roles (38)
Silicon Validation Engineer, Google Cloud
Bengaluru · On-site (inferred from location)
- SystemVerilog
- UVM
- Functional Coverage
- SVA
- +2
Not disclosed
Added by ChipJobs from Google India's careers page · Posted · 1 day ago · Checked
Senior Silicon Validation Engineer, Cloud Silicon
Bengaluru · On-site (inferred from location)
- SystemVerilog
- UVM
- Functional Coverage
- SVA
- +2
Not disclosed
Added by ChipJobs from Google India's careers page · Posted · 1 day ago · Checked
Silicon Validation Engineer, CPU
Bengaluru · On-site (inferred from location)
- SystemVerilog
- UVM
- Functional Coverage
- SVA
- +2
Not disclosed
Added by ChipJobs from Google India's careers page · Posted · 1 day ago · Checked
Silicon Validation Engineer AI/ML, Google Cloud
Bengaluru · On-site (inferred from location)
- SystemVerilog
- UVM
- Functional Coverage
- SVA
- +2
Not disclosed
Added by ChipJobs from Google India's careers page · Posted · 1 day ago · Checked
Senior Silicon Diagnostics Engineer
Bengaluru · On-site (inferred from location)
- Scan Insertion
- ATPG
- JTAG
- MBIST
- +1
Not disclosed
Added by ChipJobs from Google India's careers page · Posted · 1 day ago · Checked
Silicon DFT Engineer, PhD, Google Cloud
Bengaluru · On-site (inferred from location)
- Scan Insertion
- ATPG
- JTAG
- MBIST
- +1
Not disclosed
Added by ChipJobs from Google India's careers page · Posted · 1 day ago · Checked
Senior DFT Design Engineer, Google Cloud
Bengaluru · On-site (inferred from location)
- Scan Insertion
- ATPG
- JTAG
- MBIST
- +1
Not disclosed
Added by ChipJobs from Google India's careers page · Posted · 1 day ago · Checked
Senior DFT Design/Micro Architect Engineer, Google Cloud
Bengaluru · On-site (inferred from location)
- Scan Insertion
- ATPG
- JTAG
- MBIST
- +1
Not disclosed
Added by ChipJobs from Google India's careers page · Posted · 1 day ago · Checked
SoC DFT Technical Manager, Google Cloud
Bengaluru · On-site (inferred from location)
- Scan Insertion
- ATPG
- JTAG
- MBIST
- +1
Not disclosed
Added by ChipJobs from Google India's careers page · Posted · 1 day ago · Checked
Silicon Emulation Engineer, Google Cloud
Bengaluru · On-site (inferred from location)
- SystemVerilog
- UVM
- Functional Coverage
- SVA
- +2
Not disclosed
Added by ChipJobs from Google India's careers page · Posted · 1 day ago · Checked
Silicon Emulation Engineer III
Bengaluru · On-site (inferred from location)
- SystemVerilog
- UVM
- Functional Coverage
- SVA
- +2
Not disclosed
Added by ChipJobs from Google India's careers page · Posted · 1 day ago · Checked
Silicon Engineer, Design Verification
Bengaluru · On-site (inferred from location)
- SystemVerilog
- UVM
- Functional Coverage
- SVA
- +2
Not disclosed
Added by ChipJobs from Google India's careers page · Posted · 1 day ago · Checked
Senior Silicon Design Verification Engineer
Bengaluru · On-site (inferred from location)
- SystemVerilog
- UVM
- Functional Coverage
- SVA
- +2
Not disclosed
Added by ChipJobs from Google India's careers page · Posted · 1 day ago · Checked
Senior Silicon Design Verification Engineer, Google Cloud
Bengaluru · On-site (inferred from location)
- SystemVerilog
- UVM
- Functional Coverage
- SVA
- +2
Not disclosed
Added by ChipJobs from Google India's careers page · Posted · 1 day ago · Checked
Design Verification Engineer, Cloud Silicon
Bengaluru · On-site (inferred from location)
- SystemVerilog
- UVM
- Functional Coverage
- SVA
- +2
Not disclosed
Added by ChipJobs from Google India's careers page · Posted · 1 day ago · Checked
Design Verification Engineer, TPU, Silicon, Google Cloud
Bengaluru · On-site (inferred from location)
- SystemVerilog
- UVM
- Functional Coverage
- SVA
- +2
Not disclosed
Added by ChipJobs from Google India's careers page · Posted · 1 day ago · Checked
Senior Design Verification Engineer, Silicon, Google Cloud
Bengaluru · On-site (inferred from location)
- SystemVerilog
- UVM
- Functional Coverage
- SVA
- +2
Not disclosed
Added by ChipJobs from Google India's careers page · Posted · 1 day ago · Checked
Senior Design Verification Engineer, Google Cloud
Bengaluru · On-site (inferred from location)
- SystemVerilog
- UVM
- Functional Coverage
- SVA
- +2
Not disclosed
Added by ChipJobs from Google India's careers page · Posted · 1 day ago · Checked
Design Verification Lead, Google Cloud
Bengaluru · On-site (inferred from location)
- SystemVerilog
- UVM
- Functional Coverage
- SVA
- +2
Not disclosed
Added by ChipJobs from Google India's careers page · Posted · 1 day ago · Checked
Design Verification Engineer, PhD, Early Career
Bengaluru · On-site (inferred from location)
- SystemVerilog
- UVM
- Functional Coverage
- SVA
- +2
Not disclosed
Added by ChipJobs from Google India's careers page · Posted · 1 day ago · Checked
Silicon Formal Verification Engineer III, Cloud
Bengaluru · On-site (inferred from location)
- SystemVerilog
- UVM
- Functional Coverage
- SVA
- +2
Not disclosed
Added by ChipJobs from Google India's careers page · Posted · 1 day ago · Checked
Silicon RTL Design Engineer, PhD, Google Cloud
Bengaluru · On-site (inferred from location)
- RTL Coding
- SystemVerilog
- Verilog
- Microarchitecture
- +2
Not disclosed
Added by ChipJobs from Google India's careers page · Posted · 1 day ago · Checked
ASIC RTL Design Engineer III, Silicon
Bengaluru · On-site (inferred from location)
- RTL Coding
- SystemVerilog
- Verilog
- Microarchitecture
- +2
Not disclosed
Added by ChipJobs from Google India's careers page · Posted · 1 day ago · Checked
Digital Design Engineer, RTL IP, Silicon
Bengaluru · On-site (inferred from location)
- RTL Coding
- SystemVerilog
- Verilog
- Microarchitecture
- +2
Not disclosed
Added by ChipJobs from Google India's careers page · Posted · 1 day ago · Checked
Senior Silicon Digital Design Engineer, Core IP
Bengaluru · On-site (inferred from location)
- RTL Coding
- SystemVerilog
- Verilog
- Microarchitecture
- +2
Not disclosed
Added by ChipJobs from Google India's careers page · Posted · 1 day ago · Checked
Micro-architecture and RTL Lead, Google Cloud
Bengaluru · On-site (inferred from location)
- RTL Coding
- SystemVerilog
- Verilog
- Microarchitecture
- +2
Not disclosed
Added by ChipJobs from Google India's careers page · Posted · 1 day ago · Checked
Silicon Engineer, Custom Circuits and SRAM, Google Cloud
Bengaluru · On-site (inferred from location)
- Cadence Virtuoso
- Analog Layout
- Parasitic Extraction
- Device Physics
- +1
Not disclosed
Added by ChipJobs from Google India's careers page · Posted · 1 day ago · Checked
Circuit Design Engineer, Technology and Foundry Interface, Google Cloud
Bengaluru · On-site (inferred from location)
- Cadence Virtuoso
- Analog Layout
- Parasitic Extraction
- Device Physics
- +1
Not disclosed
Added by ChipJobs from Google India's careers page · Posted · 1 day ago · Checked
Senior Silicon Physical Design Engineer, Google Cloud
Bengaluru · On-site (inferred from location)
- Floorplanning
- Place and Route
- Timing Closure
- Physical Verification
- +1
Not disclosed
Added by ChipJobs from Google India's careers page · Posted · 1 day ago · Checked
Silicon Physical Design STA Lead, Google Cloud
Bengaluru · On-site (inferred from location)
- Static Timing Analysis
- PrimeTime
- SDC
- Timing Closure
- +1
Not disclosed
Added by ChipJobs from Google India's careers page · Posted · 1 day ago · Checked
Silicon Backend CAD Engineer III, Silicon
Bengaluru · On-site (inferred from location)
- Floorplanning
- Place and Route
- Timing Closure
- Physical Verification
- +1
Not disclosed
Added by ChipJobs from Google India's careers page · Posted · 1 day ago · Checked
Silicon CAD Engineer II
Bengaluru · On-site (inferred from location)
- C++
- Python
- Algorithms
- Software Architecture
- +1
Not disclosed
Added by ChipJobs from Google India's careers page · Posted · 1 day ago · Checked
Silicon Chip Lead, Google Cloud
Bengaluru · On-site (inferred from location)
- RTL Coding
- SystemVerilog
- Verilog
- Microarchitecture
- +2
Not disclosed
Added by ChipJobs from Google India's careers page · Posted · 1 day ago · Checked
Chip Infrastructure, Silicon Engineering
Bengaluru · On-site (inferred from location)
- C++
- Python
- Algorithms
- Software Architecture
- +1
Not disclosed
Added by ChipJobs from Google India's careers page · Posted · 1 day ago · Checked
AI/ML Hardware Architect, Cloud, Silicon
Bengaluru · On-site (inferred from location)
- RTL Coding
- SystemVerilog
- Verilog
- Microarchitecture
- +2
Not disclosed
Added by ChipJobs from Google India's careers page · Posted · 1 day ago · Checked
Senior AI/ML Hardware Architect, Google Cloud
Bengaluru · On-site (inferred from location)
- RTL Coding
- SystemVerilog
- Verilog
- Microarchitecture
- +2
Not disclosed
Added by ChipJobs from Google India's careers page · Posted · 1 day ago · Checked
Silicon Engineer, Platform and Devices, University Graduate, 2026
Bengaluru · On-site (inferred from location)
- RTL Coding
- SystemVerilog
- Verilog
- Microarchitecture
- +2
Not disclosed
Added by ChipJobs from Google India's careers page · Posted · 1 day ago · Checked
Company details are compiled from Google India’s own public pages. Every listing above links back to the employer’s original posting. There is no rating, no review count and no employer score on this page — we have no data behind one, and ratings without volume are worse than no ratings.