NVIDIA India

Fabless · 5000+ people · Bengaluru · www.nvidia.com

Publishes a salary range on 0 of the 50 most recent of 109 live roles.

India has no pay-transparency law, so almost no employer publishes a band on an Indian posting. We track this figure for every employer on the board rather than filling the gap with an estimate of our own.

Live roles (109)

N
Senior Silicon Power Engineer
Bengaluru · Hybrid
- power characterization
- post-silicon bring-up
- silicon debug/root-cause analysis
- tester-to-system correlation
- +4
- +3
Not disclosed
Added by ChipJobs from NVIDIA India's careers page · Posted 26 Aug 2026 · 3 days ago · Checked 29 Aug 2026
N
Hardware Engineer, Silicon Power and Productization
Bengaluru · Hybrid
- silicon bring-up & characterization
- power/performance modeling
- silicon binning & productization
- pre-silicon to post-silicon correlation
- +4
- +3
Not disclosed
Added by ChipJobs from NVIDIA India's careers page · Posted 26 Aug 2026 · 3 days ago · Checked 29 Aug 2026
N
Senior Formal Verification Engineer
Bengaluru · Hybrid
- formal verification
- RTL micro-architecture
- assertion-based verification
- formal testbench development
- +4
- +3
Not disclosed
Added by ChipJobs from NVIDIA India's careers page · Posted 25 Aug 2026 · 4 days ago · Checked 29 Aug 2026
N
Senior Circuit Silicon Correlation DFT Engineer
Bengaluru · Hybrid
- DFT (scan, BIST, fault models)
- ATPG pattern generation
- RTL/gate-level verification
- VCS
- +4
- +3
Not disclosed
Added by ChipJobs from NVIDIA India's careers page · Posted 25 Aug 2026 · 4 days ago · Checked 29 Aug 2026
N
IP Verification Engineer - GPU Core Pipeline
Bengaluru · Hybrid
- UVM
- SystemVerilog
- Verilog
- C++
- +5
- +4
Not disclosed
Added by ChipJobs from NVIDIA India's careers page · Posted 25 Aug 2026 · 4 days ago · Checked 29 Aug 2026
N
ASIC Design Engineer - RTL and Circuits
Bengaluru · Hybrid
- Verilog/SystemVerilog RTL design
- Mixed-signal & custom digital design
- Behavioral circuit modeling
- DFT
- +4
- +3
Not disclosed
Added by ChipJobs from NVIDIA India's careers page · Posted 24 Aug 2026 · 5 days ago · Checked 29 Aug 2026
N
ASIC Methodology, Flow and Integration Engineer
Bengaluru · Hybrid
- RTL integration
- Python
- Perl
- ASIC design methodology
- +4
- +3
Not disclosed
Added by ChipJobs from NVIDIA India's careers page · Posted 21 Aug 2026 · 8 days ago · Checked 29 Aug 2026
N
Senior Verification Engineer, PCIE
Bengaluru · Hybrid
- UVM
- SystemVerilog
- Verilog
- PCI Express (PCIe)
- +4
- +3
Not disclosed
Added by ChipJobs from NVIDIA India's careers page · Posted 20 Aug 2026 · 9 days ago · Checked 29 Aug 2026
N
Verification Engineer - PCIE
Bengaluru · Hybrid
- UVM
- SystemVerilog
- Verilog
- PCI Express (PCIe Gen3+)
- +4
- +3
Not disclosed
Added by ChipJobs from NVIDIA India's careers page · Posted 20 Aug 2026 · 9 days ago · Checked 29 Aug 2026
N
Verification Engineer - PCIE
Bengaluru · Hybrid
- UVM
- SystemVerilog
- Verilog
- PCI Express (PCIe)
- +5
- +4
Not disclosed
Added by ChipJobs from NVIDIA India's careers page · Posted 20 Aug 2026 · 9 days ago · Checked 29 Aug 2026
N
Verification Engineer - PCIE
Bengaluru · Hybrid
- UVM
- SystemVerilog
- Verilog
- PCI Express (PCIe)
- +4
- +3
Not disclosed
Added by ChipJobs from NVIDIA India's careers page · Posted 19 Aug 2026 · 10 days ago · Checked 29 Aug 2026
N
CPU Verification Engineer
Bengaluru · Hybrid
- ARM architecture verification
- CPU microarchitecture verification
- testbench development
- RIS stimulus generation
- +3
- +2
Not disclosed
Added by ChipJobs from NVIDIA India's careers page · Posted 19 Aug 2026 · 10 days ago · Checked 29 Aug 2026
N
Senior DFX Engineer - HSIO
Bengaluru · Hybrid
- DFX (Design for Test/Excellence)
- High-Speed IO (HSIO)
- Functional & structural test
- Silicon bring-up
- +5
- +4
Not disclosed
Added by ChipJobs from NVIDIA India's careers page · Posted 19 Aug 2026 · 10 days ago · Checked 29 Aug 2026
N
Senior SoC Design Engineer
Bengaluru · Hybrid
- Verilog/SystemVerilog
- AMBA AXI/AHB/APB
- SoC clock/reset/debug architecture
- USB/PCIe/SDCC peripherals
- +4
- +3
Not disclosed
Added by ChipJobs from NVIDIA India's careers page · Posted 19 Aug 2026 · 10 days ago · Checked 29 Aug 2026
N
Verification Engineer - ARM Fabric Unit Level
Bengaluru · Hybrid
- UVM
- SystemVerilog
- ARM AXI/AHB/APB
- Functional coverage
- +4
- +3
Not disclosed
Added by ChipJobs from NVIDIA India's careers page · Posted 18 Aug 2026 · 11 days ago · Checked 29 Aug 2026
N
ASIC Verification Engineer
Hyderabad · Hybrid
- SystemVerilog
- UVM
- VCS
- Formal Verification
- +4
- +3
Not disclosed
Added by ChipJobs from NVIDIA India's careers page · Posted 14 Aug 2026 · 15 days ago · Checked 29 Aug 2026
N
Senior IP Design Verification Engineer - XBAR IP
Bengaluru · Hybrid
- SystemVerilog/UVM
- Verilog
- coverage-driven verification
- assertion-based verification
- +4
- +3
Not disclosed
Added by ChipJobs from NVIDIA India's careers page · Posted 14 Aug 2026 · 15 days ago · Checked 29 Aug 2026
N
Senior IP Design Verification Engineer - XBAR IP
Bengaluru · Hybrid
- SystemVerilog/UVM
- Verilog
- coverage-driven verification
- assertion-based verification
- +4
- +3
Not disclosed
Added by ChipJobs from NVIDIA India's careers page · Posted 14 Aug 2026 · 15 days ago · Checked 29 Aug 2026
N
Senior Verification Engineer - HSIO Cluster and SOC
Bengaluru · Hybrid
- SystemVerilog
- UVM
- C/C++
- Functional Coverage
- +4
- +3
Not disclosed
Added by ChipJobs from NVIDIA India's careers page · Posted 14 Aug 2026 · 15 days ago · Checked 29 Aug 2026
N
Senior Verification Engineer
Bengaluru · Hybrid
- SystemVerilog
- Verilog
- CPU microarchitecture verification
- ARM architecture
- +4
- +3
Not disclosed
Added by ChipJobs from NVIDIA India's careers page · Posted 14 Aug 2026 · 15 days ago · Checked 29 Aug 2026
N
Senior Verification Engineer
Bengaluru · On-site
- SystemVerilog
- Verilog
- CPU microarchitecture verification
- ARM architecture
- +5
- +4
Not disclosed
Added by ChipJobs from NVIDIA India's careers page · Posted 14 Aug 2026 · 15 days ago · Checked 29 Aug 2026
N
ASIC Verification Engineer
Bengaluru · Hybrid
- SystemVerilog
- UVM
- VCS
- Formal Verification
- +4
- +3
Not disclosed
Added by ChipJobs from NVIDIA India's careers page · Posted 14 Aug 2026 · 15 days ago · Checked 29 Aug 2026
N
ASIC Verification Engineer
Hyderabad · Hybrid
- SystemVerilog
- UVM
- VCS
- Formal Verification
- +4
- +3
Not disclosed
Added by ChipJobs from NVIDIA India's careers page · Posted 14 Aug 2026 · 15 days ago · Checked 29 Aug 2026
N
Senior Verification Engineer - Hardware
Bengaluru · Hybrid
- UVM/VMM verification methodology
- C/C++ system-level verification
- Functional coverage & verification closure
- AXI/APB bus protocols
- +4
- +3
Not disclosed
Added by ChipJobs from NVIDIA India's careers page · Posted 14 Aug 2026 · 15 days ago · Checked 29 Aug 2026
N
ASIC Engineer
Bengaluru · On-site
- CDC/RDC verification
- RTL lint & structural analysis
- Verilog/SystemVerilog
- UPF low-power verification
- +4
- +3
Not disclosed
Added by ChipJobs from NVIDIA India's careers page · Posted 14 Aug 2026 · 15 days ago · Checked 29 Aug 2026
N
SOC Verification Engineer
Bengaluru · On-site
- SystemVerilog
- Verilog
- C/C++
- SOC verification
- +4
- +3
Not disclosed
Added by ChipJobs from NVIDIA India's careers page · Posted 14 Aug 2026 · 15 days ago · Checked 29 Aug 2026
N
Senior Verification Engineer - ARM Fabric Unit Level
Bengaluru · Hybrid
- UVM
- SystemVerilog
- ARM architecture (AXI/AHB/APB)
- functional coverage
- +3
- +2
Not disclosed
Added by ChipJobs from NVIDIA India's careers page · Posted 14 Aug 2026 · 15 days ago · Checked 29 Aug 2026
N
Senior Verification Engineer
Bengaluru · On-site
- SystemVerilog
- Verilog
- ARM CPU architecture
- Coherent fabric / interconnect verification
- +4
- +3
Not disclosed
Added by ChipJobs from NVIDIA India's careers page · Posted 13 Aug 2026 · 16 days ago · Checked 29 Aug 2026
N
Senior Post Silicon HSIO Bringup Lead
Bengaluru · Hybrid
- PCIe
- CXL
- NVLink
- post-silicon validation
- +5
- +4
Not disclosed
Added by ChipJobs from NVIDIA India's careers page · Posted 11 Aug 2026 · 18 days ago · Checked 29 Aug 2026
N
Senior Mask Design Engineer – Hardware
Bengaluru · On-site
- Cadence Virtuoso
- silicon interposer layout
- DRC/LVS
- Calibre
- +4
- +3
Not disclosed
Added by ChipJobs from NVIDIA India's careers page · Posted 11 Aug 2026 · 18 days ago · Checked 29 Aug 2026
N
Senior Board Design Engineer
Bengaluru · On-site (inferred from location)
- board/system design
- electrical schematics
- PCB layout
- SI/EMC
- +4
- +3
Not disclosed
Added by ChipJobs from NVIDIA India's careers page · Posted 10 Aug 2026 · 19 days ago · Checked 29 Aug 2026
N
Senior ASIC Design Engineer - XBAR IP
Bengaluru · Hybrid
- RTL Design
- Verilog
- Micro-architecture
- VCS / Debussy
- +5
- +4
Not disclosed
Added by ChipJobs from NVIDIA India's careers page · Posted 9 Aug 2026 · 20 days ago · Checked 29 Aug 2026
N
Senior Design Engineer - Memory Subsystem
Bengaluru · Hybrid
- Verilog
- RTL design
- micro-architecture
- ASIC design flow
- +5
- +4
Not disclosed
Added by ChipJobs from NVIDIA India's careers page · Posted 9 Aug 2026 · 20 days ago · Checked 29 Aug 2026
N
ASIC Design Engineer
Bengaluru · Hybrid
- RTL design
- Verilog/SystemVerilog
- micro-architecture definition
- synthesis & lint
- +5
- +4
Not disclosed
Added by ChipJobs from NVIDIA India's careers page · Posted 9 Aug 2026 · 20 days ago · Checked 29 Aug 2026
N
Senior SOC Design Engineer - Networking Group
Bengaluru · Hybrid
- Verilog/SV
- Cadence simulation
- RTL Design
- ASIC Architecture & Micro-Architecture
- +5
- +4
Not disclosed
Added by ChipJobs from NVIDIA India's careers page · Posted 9 Aug 2026 · 20 days ago · Checked 29 Aug 2026
N
Senior SOC Design Engineer - Networking Group
Bengaluru · Hybrid
- SOC design & integration
- RTL design (Verilog/SystemVerilog)
- ASIC architecture & micro-architecture
- Timing closure
- +4
- +3
Not disclosed
Added by ChipJobs from NVIDIA India's careers page · Posted 9 Aug 2026 · 20 days ago · Checked 29 Aug 2026
N
Verification Engineer - HWPM
Bengaluru · Hybrid
- SystemVerilog
- UVM
- Python scripting
- VCS
- +5
- +4
Not disclosed
Added by ChipJobs from NVIDIA India's careers page · Posted 8 Aug 2026 · 21 days ago · Checked 29 Aug 2026
N
Verification Engineer - GPU Fullchip
Bengaluru · Hybrid
- Verilog
- SystemVerilog
- UVM/VMM
- C/C++
- +4
- +3
Not disclosed
Added by ChipJobs from NVIDIA India's careers page · Posted 8 Aug 2026 · 21 days ago · Checked 29 Aug 2026
N
Verification Engineer - GPU Fullchip
Bengaluru · Hybrid
- Verilog
- SystemVerilog
- UVM/VMM
- C/C++
- +4
- +3
Not disclosed
Added by ChipJobs from NVIDIA India's careers page · Posted 8 Aug 2026 · 21 days ago · Checked 29 Aug 2026
N
PCIe IP Verification Engineer
Bengaluru · Hybrid
- UVM
- SystemVerilog
- Verilog
- PCI Express (PCIe Gen3+)
- +4
- +3
Not disclosed
Added by ChipJobs from NVIDIA India's careers page · Posted 8 Aug 2026 · 21 days ago · Checked 29 Aug 2026
N
Verification Engineer - PCIE
Bengaluru · Hybrid
- UVM
- SystemVerilog
- Verilog
- PCI Express (PCIe)
- +5
- +4
Not disclosed
Added by ChipJobs from NVIDIA India's careers page · Posted 8 Aug 2026 · 21 days ago · Checked 29 Aug 2026
N
IP Verification Engineer - GPU Core Pipeline
Bengaluru · Hybrid
- UVM
- SystemVerilog
- Verilog
- C++
- +5
- +4
Not disclosed
Added by ChipJobs from NVIDIA India's careers page · Posted 8 Aug 2026 · 21 days ago · Checked 29 Aug 2026
N
Senior Memory Subsystem Architect
Bengaluru · Hybrid
- SoC architecture
- memory subsystem design
- MMU / address translation
- DRAM controllers
- +4
- +3
Not disclosed
Added by ChipJobs from NVIDIA India's careers page · Posted 7 Aug 2026 · 22 days ago · Checked 29 Aug 2026
N
Power Architecture Engineer
Bengaluru · Hybrid
- UPF power intent
- Power-aware verification
- Low-power design (multi-VT, clock/power gating, DVFS)
- Verilog
- +4
- +3
Not disclosed
Added by ChipJobs from NVIDIA India's careers page · Posted 31 Jul 2026 · 29 days ago · Checked 29 Aug 2026
N
Power Architecture Engineer
Bengaluru · Hybrid
- UPF power intent
- Power-aware verification
- Low-power design (multi-VT, clock/power gating, DVFS)
- Verilog
- +4
- +3
Not disclosed
Added by ChipJobs from NVIDIA India's careers page · Posted 31 Jul 2026 · 29 days ago · Checked 29 Aug 2026
N
Power Architecture Engineer
Bengaluru · Hybrid
- UPF power intent
- Power-aware verification
- Low-power design (multi-VT, clock/power gating, DVFS)
- Verilog
- +4
- +3
Not disclosed
Added by ChipJobs from NVIDIA India's careers page · Posted 31 Jul 2026 · 29 days ago · Checked 29 Aug 2026
N
Senior Packaging Technical Engineer - Hardware
Bengaluru · Hybrid
- package layout design
- pad ring / floor plan definition
- substrate interconnect / ball-out
- signal integrity
- +5
- +4
Not disclosed
Added by ChipJobs from NVIDIA India's careers page · Posted 31 Jul 2026 · 29 days ago · Checked 29 Aug 2026
N
High Speed IO Validation Engineer
Bengaluru · Hybrid
- PCIe / NVLink / UCIe protocols
- SERDES characterization
- Signal & power integrity (S-parameters, eye diagrams, jitter)
- Lab instrumentation (BERT, VNA, DSO, TDR)
- +4
- +3
Not disclosed
Added by ChipJobs from NVIDIA India's careers page · Posted 29 Jul 2026 · 31 days ago · Checked 29 Aug 2026
N
Senior Architect, GPU and SoC Modelling
Bengaluru · Hybrid
- C++
- SystemC
- TLM modeling
- CMake/Make
- +5
- +4
Not disclosed
Added by ChipJobs from NVIDIA India's careers page · Posted 28 Jul 2026 · 32 days ago · Checked 29 Aug 2026
N
Senior Verification Engineer, Emulation and Prototyping
Bengaluru · Hybrid
- FPGA prototyping & hardware emulation (Synopsys ZeBu, Siemens Veloce, Cadence Z3)
- SV/Verilog testbench development
- C/C++ emulation testbenches & transactors
- DPI/PLI/SystemC interfaces
- +4
- +3
Not disclosed
Added by ChipJobs from NVIDIA India's careers page · Posted 27 Jul 2026 · 33 days ago · Checked 29 Aug 2026

Company details are compiled from NVIDIA India’s own public pages. Every listing above links back to the employer’s original posting. There is no rating, no review count and no employer score on this page — we have no data behind one, and ratings without volume are worse than no ratings.