Principal Digital Design Engineer
ON Semiconductor India · Bangalore · On-site (inferred from location)
- Pay
- Not disclosed
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- Work setup
- On-site (inferred from location)
- Employment
- Full-time (inferred)
- Discipline
- RTL Design
Skills
- RTL Design
- CDC (Clock Domain Crossing)
- ASIC Synthesis
- Static Timing Analysis
- UPF / Low-Power Design
- SystemVerilog Assertions
- Verilog / TCL / Perl / Python
Added by ChipJobs from ON Semiconductor India's careers page · Posted · 9 days ago · Checked
About the role
Leads digital design architecture, RTL implementation, synthesis, and timing analysis for onsemi's Power Management ICs (DC-DC PMIC/POL, multiphase controllers, AC-DC converters, LED/SiC drivers) out of Bengaluru, collaborating with analog design and verification teams across pre-silicon bring-up (SoCV, emulation, FPGA) through post-silicon validation.
How we checked this listing
| What we checked | Result | When |
|---|---|---|
| Is this a real posting on the employer's own site? | Opened by hand on ON Semiconductor India's own careers page and entered here. It was live at the time. | 29 Aug 2026 |
| Who put it here? | We found this on ON Semiconductor India's careers page and entered it by hand. The employer has not confirmed it with us. | — |
| Does it have a salary range? | No. The employer does not publish a pay band on this posting. | — |
| Is it still live today? | We have not completed a source re-check since it was entered by hand. It remains marked unchecked. | 29 Aug 2026 |
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