Senior Principal Digital Design Engineer, Power Management
ON Semiconductor India · Bangalore · On-site (inferred from location)
- Pay
- Not disclosed
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- Work setup
- On-site (inferred from location)
- Employment
- Full-time (inferred)
- Discipline
- RTL Design
Skills
- RTL design
- CDC (clock domain crossing)
- ASIC synthesis
- static timing analysis
- Place & Route (P&R)
- UPF (power intent)
- SystemVerilog assertions
Added by ChipJobs from ON Semiconductor India's careers page · Posted · 9 days ago · Checked
About the role
Senior digital design engineer role in onsemi's Power Management new-product-development group in Bengaluru, building DC-DC PMIC/POL, multiphase controllers, Dr.MOS, AC-DC converters, LED/SiC drivers, switches, and efuses for consumer, industrial, and automotive applications. The role spans RTL design and digital architecture through synthesis, timing/CDC analysis, and P&R, collaborating with both analog and digital teams across the end-to-end ASIC/mixed-signal chip development flow.
How we checked this listing
| What we checked | Result | When |
|---|---|---|
| Is this a real posting on the employer's own site? | Opened by hand on ON Semiconductor India's own careers page and entered here. It was live at the time. | 29 Aug 2026 |
| Who put it here? | We found this on ON Semiconductor India's careers page and entered it by hand. The employer has not confirmed it with us. | — |
| Does it have a salary range? | No. The employer does not publish a pay band on this posting. | — |
| Is it still live today? | We have not completed a source re-check since it was entered by hand. It remains marked unchecked. | 29 Aug 2026 |
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