Renesas Electronics India

IDM · 5000+ people · Bengaluru · www.renesas.com

Publishes a salary range on 0 of the 50 most recent of 99 live roles.

India has no pay-transparency law, so almost no employer publishes a band on an Indian posting. We track this figure for every employer on the board rather than filling the gap with an estimate of our own.

Live roles (99)

R
Principal Analog Engineer
Bengaluru · On-site (inferred from location)
- PMIC / DC-DC converter design
- switching converter control loops
- charge pumps & LDOs
- SAR ADC / bandgap / op-amp design
- +4
- +3
Not disclosed
Added by ChipJobs from Renesas Electronics India's careers page · Posted 26 Aug 2026 · 3 days ago · Checked 29 Aug 2026
R
Director Engineering, Analog Design (Power ICs)
Bengaluru · On-site (inferred from location)
- mixed-signal IC design
- analog IC architecture
- power IC design
- automotive IC qualification
- +5
- +4
Not disclosed
Added by ChipJobs from Renesas Electronics India's careers page · Posted 25 Aug 2026 · 4 days ago · Checked 29 Aug 2026
R
Sr Staff Engineer, STA
Bengaluru · On-site (inferred from location)
- Static Timing Analysis (STA)
- Logic Synthesis
- SDC/UPF Constraints
- Fusion Compiler
- +5
- +4
Not disclosed
Added by ChipJobs from Renesas Electronics India's careers page · Posted 25 Aug 2026 · 4 days ago · Checked 29 Aug 2026
R
Principal Digital Engineer (DFT Design)
Bengaluru · Hybrid (inferred from location)
- DFT/Scan insertion
- ATPG
- LBIST
- RTL/Verilog/SystemVerilog
- +5
- +4
Not disclosed
Added by ChipJobs from Renesas Electronics India's careers page · Posted 24 Aug 2026 · 5 days ago · Checked 29 Aug 2026
R
Sr Staff Engineer – Analog/Mixed-Signal Design
Indiranagar · On-site (inferred from location)
- transistor-level analog IC design
- power management ICs (LDO/charge pump)
- SAR ADC design
- bandgap references & op-amps
- +4
- +3
Not disclosed
Added by ChipJobs from Renesas Electronics India's careers page · Posted 24 Aug 2026 · 5 days ago · Checked 29 Aug 2026
R
Staff/ Sr Staff Engineer, Digital Design
Bengaluru · On-site (inferred from location)
- RTL Design
- Verilog/VHDL
- Micro-architecture Design
- SoC Integration
- +5
- +4
Not disclosed
Added by ChipJobs from Renesas Electronics India's careers page · Posted 24 Aug 2026 · 5 days ago · Checked 29 Aug 2026
R
Principal Engineer, Digital Design
Bengaluru · On-site (inferred from location)
- RTL Design (Verilog/VHDL)
- Micro-architecture Definition
- Static Timing Analysis
- Lint/CDC/RDC (Spyglass)
- +4
- +3
Not disclosed
Added by ChipJobs from Renesas Electronics India's careers page · Posted 24 Aug 2026 · 5 days ago · Checked 29 Aug 2026
R
Principal ATE Test Engineer
Bengaluru · On-site (inferred from location)
- ATE test development
- COHU DMDX/DXV
- Accotest
- DFT techniques
- +4
- +3
Not disclosed
Added by ChipJobs from Renesas Electronics India's careers page · Posted 24 Aug 2026 · 5 days ago · Checked 29 Aug 2026
R
Senior Staff Engineer, Analog Design (Power & Analog ICs)
Bengaluru · On-site (inferred from location)
- switching converter design (buck/boost/buck-boost)
- LDO and charge pump design
- control-loop compensation & stability analysis
- SAR ADC and voltage/current reference design
- +4
- +3
Not disclosed
Added by ChipJobs from Renesas Electronics India's careers page · Posted 21 Aug 2026 · 8 days ago · Checked 29 Aug 2026
R
Senior Staff Engineer, Digital Design (Power & Analog ICs)
Bengaluru · On-site (inferred from location)
- Verilog/SystemVerilog RTL
- digital microarchitecture
- synthesis & lint
- static timing analysis (STA)
- +4
- +3
Not disclosed
Added by ChipJobs from Renesas Electronics India's careers page · Posted 21 Aug 2026 · 8 days ago · Checked 29 Aug 2026
R
Staff Validation Engineer, Silicon Validation (DC-DC Converters)
Bengaluru · Hybrid (inferred from location)
- Post-Silicon Validation
- DC-DC Converter Characterization
- Power Management ICs (Buck/Boost/LDO/Gate Drivers)
- PCB Schematic & Layout Review
- +4
- +3
Not disclosed
Added by ChipJobs from Renesas Electronics India's careers page · Posted 21 Aug 2026 · 8 days ago · Checked 29 Aug 2026
R
Senior Staff Validation Engineer, Silicon Validation (DC-DC Converters)
Bengaluru · Hybrid (inferred from location)
- DC-DC converter validation (Buck/Boost/LDO/gate drivers)
- post-silicon bring-up & characterization
- bench debug: oscilloscopes, SMUs, spectrum/network analyzers
- PCB schematic & layout review
- +4
- +3
Not disclosed
Added by ChipJobs from Renesas Electronics India's careers page · Posted 21 Aug 2026 · 8 days ago · Checked 29 Aug 2026
R
Validation Engineer
Bengaluru · On-site (inferred from location)
- Python for lab automation
- analog/mixed-signal IC validation
- power management ICs
- PCB schematic design (board-level)
- +4
- +3
Not disclosed
Added by ChipJobs from Renesas Electronics India's careers page · Posted 20 Aug 2026 · 9 days ago · Checked 29 Aug 2026
R
Sr Staff Test Engineer - ATE
Bengaluru · On-site (inferred from location)
- ATE test program development
- Advantest 93K / Cohu DiamondX / SPEA / Teradyne Eagle
- I2C/I3C/SPI protocol testing
- STDF data analysis (Spotfire/dataPower)
- +4
- +3
Not disclosed
Added by ChipJobs from Renesas Electronics India's careers page · Posted 20 Aug 2026 · 9 days ago · Checked 29 Aug 2026
R
Staff Engineer, Analog Design
Bengaluru · On-site (inferred from location)
- Analog IC design
- Transistor-level design
- PMIC design
- DC-DC converters
- +5
- +4
Not disclosed
Added by ChipJobs from Renesas Electronics India's careers page · Posted 20 Aug 2026 · 9 days ago · Checked 29 Aug 2026
R
Sr Engineer, Design Verification
Bengaluru · On-site (inferred from location)
- SystemVerilog
- UVM
- functional coverage
- code coverage
- +5
- +4
Not disclosed
Added by ChipJobs from Renesas Electronics India's careers page · Posted 19 Aug 2026 · 10 days ago · Checked 29 Aug 2026
R
Staff AMS Verification Engineer
Bengaluru · On-site (inferred from location)
- AMS Verification
- PMIC
- SystemVerilog/UVM
- Real Number Modeling (RNM)
- +4
- +3
Not disclosed
Added by ChipJobs from Renesas Electronics India's careers page · Posted 19 Aug 2026 · 10 days ago · Checked 29 Aug 2026
R
Principal Engineer, DFT
Hyderabad · On-site (inferred from location)
- Tessent
- ATPG
- Scan Insertion
- MBIST/LBIST
- +4
- +3
Not disclosed
Added by ChipJobs from Renesas Electronics India's careers page · Posted 18 Aug 2026 · 11 days ago · Checked 29 Aug 2026
R
Staff Engineer, Analog Design
Bengaluru · On-site (inferred from location)
- Analog IC Design
- Circuit Design
- Semiconductor Design
- Analog/Mixed-Signal
- +1
Not disclosed
Added by ChipJobs from Renesas Electronics India's careers page · Posted 17 Aug 2026 · 12 days ago · Checked 29 Aug 2026
R
ATE Test Engineer
Bengaluru · On-site (inferred from location)
- ATE test development
- C/C++ test programs
- Python
- DFT concepts
- +4
- +3
Not disclosed
Added by ChipJobs from Renesas Electronics India's careers page · Posted 17 Aug 2026 · 12 days ago · Checked 29 Aug 2026
R
Staff Engineer, Performance Modelling
Noida · On-site (inferred from location)
- SystemC TLM 2.0
- SoC performance modeling
- performance simulation and analysis
- DDR/CPU/GPU/interconnect architecture
- +4
- +3
Not disclosed
Added by ChipJobs from Renesas Electronics India's careers page · Posted 14 Aug 2026 · 15 days ago · Checked 29 Aug 2026
R
Senior Staff Analog Design Engineer
Bengaluru · On-site (inferred from location)
- Analog IC Design
- PMIC / Power Management ICs
- Buck/Boost DC-DC Converter Design
- LDO & Charge Pump Design
- +4
- +3
Not disclosed
Added by ChipJobs from Renesas Electronics India's careers page · Posted 13 Aug 2026 · 16 days ago · Checked 29 Aug 2026
R
Senior Staff Engineer, Physical Design
Bengaluru · On-site (inferred from location)
- ICC2
- Fusion Compiler
- PrimeTime
- Cadence Innovus
- +5
- +4
Not disclosed
Added by ChipJobs from Renesas Electronics India's careers page · Posted 13 Aug 2026 · 16 days ago · Checked 29 Aug 2026
R
Sr Principal Engineer, MCU Chip Lead
Noida · On-site (inferred from location)
- SoC Architecture
- MCU Architecture
- SERDES
- Interconnect Design
- +4
- +3
Not disclosed
Added by ChipJobs from Renesas Electronics India's careers page · Posted 13 Aug 2026 · 16 days ago · Checked 29 Aug 2026
R
Sr Principal Engineer, MCU Architect
Noida · On-site (inferred from location)
- SOC/MCU architecture
- automotive SOC / SDV
- tapeout readiness
- IP make/buy selection
- +4
- +3
Not disclosed
Added by ChipJobs from Renesas Electronics India's careers page · Posted 13 Aug 2026 · 16 days ago · Checked 29 Aug 2026
R
Principal Engineer, SoC Architect
Bengaluru · On-site (inferred from location)
- SoC/MCU architecture
- RTL design
- Design verification
- RTL-to-GDSII flow
- +4
- +3
Not disclosed
Added by ChipJobs from Renesas Electronics India's careers page · Posted 12 Aug 2026 · 17 days ago · Checked 29 Aug 2026
R
Principal Engineer- Custom Layout (High-Speed Interface IP)
Bengaluru · On-site (inferred from location)
- custom layout
- floorplanning
- DRC/LVS/ERC/PERC signoff
- EMIR analysis
- +5
- +4
Not disclosed
Added by ChipJobs from Renesas Electronics India's careers page · Posted 12 Aug 2026 · 17 days ago · Checked 29 Aug 2026
R
Senior Staff Engineer – Analog/Mixed-Signal Design
Bengaluru · On-site (inferred from location)
- analog/mixed-signal IC design
- power management ICs (LDO, charge pump, SAR ADC)
- bandgap reference & op-amp design
- ESD/latch-up & chip-level protection
- +4
- +3
Not disclosed
Added by ChipJobs from Renesas Electronics India's careers page · Posted 12 Aug 2026 · 17 days ago · Checked 29 Aug 2026
R
Staff Engineer, Physical Design
Bengaluru · On-site (inferred from location)
- timing closure
- congestion analysis
- power integrity / low-power implementation
- clock tree synthesis and clock domain partitioning
- +4
- +3
Not disclosed
Added by ChipJobs from Renesas Electronics India's careers page · Posted 10 Aug 2026 · 19 days ago · Checked 29 Aug 2026
R
Sr Staff Engineer, Design Verification
Bengaluru · On-site (inferred from location)
- SystemVerilog
- UVM
- Mixed-Signal Verification
- Cadence SKILL
- +4
- +3
Not disclosed
Added by ChipJobs from Renesas Electronics India's careers page · Posted 10 Aug 2026 · 19 days ago · Checked 29 Aug 2026
R
Senior Principal Engineer- SoC/Chip Lead
Bengaluru · On-site (inferred from location)
- SoC architecture
- RTL design
- Design verification
- Physical design
- +4
- +3
Not disclosed
Added by ChipJobs from Renesas Electronics India's careers page · Posted 10 Aug 2026 · 19 days ago · Checked 29 Aug 2026
R
Sr Staff Mask Design Engineer
Bengaluru · On-site (inferred from location)
- Cadence Virtuoso/Virtuoso XL
- Mentor Graphics Calibre (DRC/LVS/PEX/DFM)
- Analog/Mixed-Signal IC Layout
- Floorplanning
- +5
- +4
Not disclosed
Added by ChipJobs from Renesas Electronics India's careers page · Posted 7 Aug 2026 · 22 days ago · Checked 29 Aug 2026
R
Senior Staff Engineer, Analog Design
Bengaluru · On-site (inferred from location)
- Analog IC Design
- PMIC / DC-DC Converter Design
- LDO & Charge Pump Design
- Control Loop Compensation
- +5
- +4
Not disclosed
Added by ChipJobs from Renesas Electronics India's careers page · Posted 6 Aug 2026 · 23 days ago · Checked 29 Aug 2026
R
Principal Engineer-Physical Design
Bengaluru · On-site (inferred from location)
- Floorplanning & Power Planning
- Clock Tree Synthesis (CTS)
- Timing Closure
- Signal Integrity / IR-EM Closure
- +4
- +3
Not disclosed
Added by ChipJobs from Renesas Electronics India's careers page · Posted 5 Aug 2026 · 24 days ago · Checked 29 Aug 2026
R
Principal Engineer- Digital Design
Bengaluru · On-site (inferred from location)
- RTL Design
- Verilog/SystemVerilog
- SoC Architecture
- Network-on-Chip (NoC)
- +4
- +3
Not disclosed
Added by ChipJobs from Renesas Electronics India's careers page · Posted 5 Aug 2026 · 24 days ago · Checked 29 Aug 2026
R
Principal Engineer- Design Verification
Bengaluru · On-site (inferred from location)
- SystemVerilog
- UVM
- SVA (Assertion-Based Verification)
- Functional & Code Coverage
- +4
- +3
Not disclosed
Added by ChipJobs from Renesas Electronics India's careers page · Posted 5 Aug 2026 · 24 days ago · Checked 29 Aug 2026
R
Principal Firmware/Middleware Architect
Bengaluru · On-site (inferred from location)
- C (bare-metal/RTOS)
- Python
- UALink/NVLink/CXL/PCIe Gen5/6
- Credit-based flow control & SerDes/PHY
- +4
- +3
Not disclosed
Added by ChipJobs from Renesas Electronics India's careers page · Posted 5 Aug 2026 · 24 days ago · Checked 29 Aug 2026
R
Senior Manager - SoC Validation
Hyderabad · On-site (inferred from location)
- ATE (Advantest/Teradyne)
- PVT bench characterization
- Wafer probe/CP yield analysis
- Silicon bring-up & debug
- +4
- +3
Not disclosed
Added by ChipJobs from Renesas Electronics India's careers page · Posted 3 Aug 2026 · 26 days ago · Checked 29 Aug 2026
R
Senior Package Design Engineer
Bengaluru · On-site (inferred from location)
- Cadence Allegro Package Designer (APD/SiP)
- Siemens Xpedition / Innovator 3D IC
- 2.5D/3D IC & chiplet packaging
- FCBGA/SiP substrate & RDL layout
- +4
- +3
Not disclosed
Added by ChipJobs from Renesas Electronics India's careers page · Posted 30 Jul 2026 · 30 days ago · Checked 29 Aug 2026
R
Senior Staff Engineer, Product Definer (IC Architect)
Bengaluru · On-site (inferred from location)
- Battery Management Systems (BMS)
- power management IC product definition
- board-level analog/digital circuit design
- SIMPLIS circuit simulation
- +5
- +4
Not disclosed
Added by ChipJobs from Renesas Electronics India's careers page · Posted 29 Jul 2026 · 31 days ago · Checked 29 Aug 2026
R
Senior/ Staff Signal and Power Integrity Engineer
Bengaluru · On-site (inferred from location)
- Signal Integrity (SI) Analysis
- Power Integrity (PI) / PDN Analysis
- ANSYS HFSS / SI-Wave EM Simulation
- Cadence PowerSI / PowerDC
- +4
- +3
Not disclosed
Added by ChipJobs from Renesas Electronics India's careers page · Posted 27 Jul 2026 · 33 days ago · Checked 29 Aug 2026
R
Sr. System Validation Manager
Bengaluru · On-site (inferred from location)
- SoC bring-up & silicon debug
- System/use-case & subsystem validation
- Coverage planning and closure
- Protocol validation (I3C/I2C/SPI/PCIe/USB/DDR/LPDDR/MIPI)
- +4
- +3
Not disclosed
Added by ChipJobs from Renesas Electronics India's careers page · Posted 25 Jul 2026 · 35 days ago · Checked 29 Aug 2026
R
Staff Engineer - Design Verification
Bengaluru · On-site (inferred from location)
- UVM
- SystemVerilog
- Verilog
- Mixed-signal verification
- +4
- +3
Not disclosed
Added by ChipJobs from Renesas Electronics India's careers page · Posted 24 Jul 2026 · 36 days ago · Checked 29 Aug 2026
R
Mgr/Sr Mgr, Application Engineering - MPU
Bengaluru · On-site (inferred from location)
- MPU
- Linux
- RTOS
- embedded systems
- +5
- +4
Not disclosed
Added by ChipJobs from Renesas Electronics India's careers page · Posted 24 Jul 2026 · 36 days ago · Checked 29 Aug 2026
R
Senior/Staff/Sr Staff Engineer, Validation
Bengaluru · On-site (inferred from location)
- Bench Validation
- Silicon Debug (PMIC)
- ATE-Bench Correlation
- Python/LabVIEW test automation
- +5
- +4
Not disclosed
Added by ChipJobs from Renesas Electronics India's careers page · Posted 24 Jul 2026 · 36 days ago · Checked 29 Aug 2026
R
Principal Engineer - Design Verification
Hyderabad · On-site (inferred from location)
- UVM
- SystemVerilog/Verilog
- AHB/AXI protocols
- formal verification
- +4
- +3
Not disclosed
Added by ChipJobs from Renesas Electronics India's careers page · Posted 21 Jul 2026 · 39 days ago · Checked 29 Aug 2026
R
Principal Engineer - Design Verification
Hyderabad · On-site (inferred from location)
- UVM
- SystemVerilog/Verilog
- AHB/AXI protocols
- formal verification
- +4
- +3
Not disclosed
Added by ChipJobs from Renesas Electronics India's careers page · Posted 21 Jul 2026 · 39 days ago · Checked 29 Aug 2026
R
Staff Engineer, Analog Design
Bengaluru · On-site (inferred from location)
- Analog IC Design
- Circuit Design
- Semiconductor Design
- Analog/Mixed-Signal
- +1
Not disclosed
Added by ChipJobs from Renesas Electronics India's careers page · Posted 20 Jul 2026 · 40 days ago · Checked 29 Aug 2026
R
Principal Engineer, RTL Design
Noida · On-site (inferred from location)
- Verilog/SystemVerilog RTL design
- AMBA AXI/AHB/APB
- UPF low-power design
- CDC/RDC methodology
- +4
- +3
Not disclosed
Added by ChipJobs from Renesas Electronics India's careers page · Posted 17 Jul 2026 · 43 days ago · Checked 29 Aug 2026
R
Sr Staff /Staff Engineer, RTL Design
Noida · On-site (inferred from location)
- RTL design
- SoC micro-architecture
- PCIe/UCIe protocols
- SERDES PCS/PMA
- +5
- +4
Not disclosed
Added by ChipJobs from Renesas Electronics India's careers page · Posted 17 Jul 2026 · 43 days ago · Checked 29 Aug 2026

Company details are compiled from Renesas Electronics India’s own public pages. Every listing above links back to the employer’s original posting. There is no rating, no review count and no employer score on this page — we have no data behind one, and ratings without volume are worse than no ratings.