Principal Engineer- Custom Layout (High-Speed Interface IP)
Renesas Electronics India · Bengaluru · On-site (inferred from location)
- Pay
- Not disclosed
Tell us what this pays
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- Work setup
- On-site (inferred from location)
- Employment
- Full-time (inferred)
- Discipline
- Physical Design
Skills
- custom layout
- floorplanning
- DRC/LVS/ERC/PERC signoff
- EMIR analysis
- analog/mixed-signal layout
- SerDes (PLL, CDR, DFE, CTLE, DLL)
- device matching
- parasitic extraction
Added by ChipJobs from Renesas Electronics India's careers page · Posted · 17 days ago · Checked
About the role
Principal custom layout engineer leading physical implementation and signoff of high-speed analog/mixed-signal SerDes building blocks (DFE, CTLE, PLL, CDR, DLL, transmitters/receivers) in advanced 5nm/3nm nodes, working closely with Analog Design, Digital Design, SI, Packaging and Product Engineering through tapeout and silicon bring-up.
How we checked this listing
| What we checked | Result | When |
|---|---|---|
| Is this a real posting on the employer's own site? | Opened by hand on Renesas Electronics India's own careers page and entered here. It was live at the time. | 29 Aug 2026 |
| Who put it here? | We found this on Renesas Electronics India's careers page and entered it by hand. The employer has not confirmed it with us. | — |
| Does it have a salary range? | No. The employer does not publish a pay band on this posting. | — |
| Is it still live today? | We have not completed a source re-check since it was entered by hand. It remains marked unchecked. | 29 Aug 2026 |
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Originally posted on the employer's careers page by Renesas Electronics India. ChipJobs links to the employer’s own posting and reproduces no content from LinkedIn, Indeed, Glassdoor or Naukri.
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