CAD Layout Design Engineer
NVIDIA India · Bengaluru · On-site (inferred from location)
- Pay
- Not disclosed
Tell us what this pays
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- Work setup
- On-site (inferred from location)
- Employment
- Full-time (inferred)
- Discipline
- EDA Software
Skills
- Cadence SKILL
- PCELL development
- SRAM/analog layout
- Python
- Perl
- EMIR/DFM guideline development
- advanced-node tapeout (5/3/2nm)
Added by ChipJobs from NVIDIA India's careers page · Posted · 197 days ago · Checked
About the role
CAD engineer on NVIDIA's Layout Methodology team, building the internal PCELL, SRAM leaf-cell and productivity-scripting infrastructure (in Cadence SKILL, Python, Perl) that enables SRAM and custom analog layout design on advanced nodes, while translating new-node characterization into EMIR/DFM/SRAM layout guidelines for other design teams.
How we checked this listing
| What we checked | Result | When |
|---|---|---|
| Is this a real posting on the employer's own site? | Opened by hand on NVIDIA India's own careers page and entered here. It was live at the time. | 29 Aug 2026 |
| Who put it here? | We found this on NVIDIA India's careers page and entered it by hand. The employer has not confirmed it with us. | — |
| Does it have a salary range? | No. The employer does not publish a pay band on this posting. | — |
| Is it still live today? | The employer source returned the matching requisition. | 29 Aug 2026 |
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Originally posted on the employer's careers page by NVIDIA India. ChipJobs links to the employer’s own posting and reproduces no content from LinkedIn, Indeed, Glassdoor or Naukri.
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