Senior ASIC Design Engineer - NOC IP
NVIDIA India · Bengaluru · Hybrid
- Pay
- Not disclosed
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- Work setup
- Hybrid
- Employment
- Full-time (inferred)
- Discipline
- RTL Design
Skills
- RTL design (Verilog)
- micro-architecture definition
- ASIC design flow (synthesis, DFT, timing, floorplanning)
- VCS / simulation & debug tools (Debussy)
- post-silicon bring-up & lab debug
- Python/Perl/shell scripting
- memory subsystem / interconnect IP
Added by ChipJobs from NVIDIA India's careers page · Posted · 135 days ago · Checked
About the role
RTL design engineer on NVIDIA's Graphics team building memory subsystem components for GPUs, owning micro-architecture and RTL development and working with verification, timing, and physical design teams to deliver synthesis/timing-clean, fully verified designs through post-silicon bring-up.
How we checked this listing
| What we checked | Result | When |
|---|---|---|
| Is this a real posting on the employer's own site? | Opened by hand on NVIDIA India's own careers page and entered here. It was live at the time. | 29 Aug 2026 |
| Who put it here? | We found this on NVIDIA India's careers page and entered it by hand. The employer has not confirmed it with us. | — |
| Does it have a salary range? | No. The employer does not publish a pay band on this posting. | — |
| Is it still live today? | The employer source returned the matching requisition. | 29 Aug 2026 |
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Originally posted on the employer's careers page by NVIDIA India. ChipJobs links to the employer’s own posting and reproduces no content from LinkedIn, Indeed, Glassdoor or Naukri.
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