Senior DFT Verification Engineer
NVIDIA India · Bengaluru · Hybrid
- Pay
- Not disclosed
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- Work setup
- Hybrid
- Employment
- Full-time (inferred)
- Discipline
- DFT
Skills
- JTAG/Boundary Scan (IEEE 1149.1/1500/1687/1838)
- Scan ATPG
- BIST architecture
- Static Timing Analysis
- RTL and Gates verification
- Silicon bring-up
- Perl/Python scripting
Added by ChipJobs from NVIDIA India's careers page · Posted · 128 days ago · Checked
About the role
DFT verification engineer on NVIDIA's Bangalore DFX team, taking end-to-end ownership of DFX verification, pattern development, and silicon bring-up for test features such as JTAG, boundary scan, security mechanisms, and reliability tests (HTOL/IDDQ) across multiple ATPG configurations in multi-die environments.
How we checked this listing
| What we checked | Result | When |
|---|---|---|
| Is this a real posting on the employer's own site? | Opened by hand on NVIDIA India's own careers page and entered here. It was live at the time. | 29 Aug 2026 |
| Who put it here? | We found this on NVIDIA India's careers page and entered it by hand. The employer has not confirmed it with us. | — |
| Does it have a salary range? | No. The employer does not publish a pay band on this posting. | — |
| Is it still live today? | The employer source returned the matching requisition. | 29 Aug 2026 |
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Originally posted on the employer's careers page by NVIDIA India. ChipJobs links to the employer’s own posting and reproduces no content from LinkedIn, Indeed, Glassdoor or Naukri.
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