Verification Engineer - Networking IPs
NVIDIA India · Bengaluru · Hybrid
- Pay
- Not disclosed
Tell us what this pays
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- Work setup
- Hybrid
- Employment
- Full-time (inferred)
- Discipline
- Design Verification
Skills
- Specman
- UVM
- SystemVerilog
- functional coverage
- testbench architecture / BFMs
- networking datapath & switching verification
- formal verification
Added by ChipJobs from NVIDIA India's careers page · Posted · 58 days ago · Checked
About the role
Verification engineer in NVIDIA's networking group, owning unit- and cluster-level verification of networking IP for datacenter chips and systems. Builds Specman/UVM testbenches, bus functional models, monitors, checkers, scoreboards, and functional coverage for queuing and scheduling sub-systems, working with architects, designers, FPGA, and post-silicon teams.
How we checked this listing
| What we checked | Result | When |
|---|---|---|
| Is this a real posting on the employer's own site? | Opened by hand on NVIDIA India's own careers page and entered here. It was live at the time. | 29 Aug 2026 |
| Who put it here? | We found this on NVIDIA India's careers page and entered it by hand. The employer has not confirmed it with us. | — |
| Does it have a salary range? | No. The employer does not publish a pay band on this posting. | — |
| Is it still live today? | The employer source returned the matching requisition. | 29 Aug 2026 |
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Originally posted on the employer's careers page by NVIDIA India. ChipJobs links to the employer’s own posting and reproduces no content from LinkedIn, Indeed, Glassdoor or Naukri.
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