Principal Engineer, Performance Modelling
Renesas Electronics India · Noida · On-site (inferred from location)
- Pay
- Not disclosed
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- Work setup
- On-site (inferred from location)
- Employment
- Full-time (inferred)
- Discipline
- Design Verification
Skills
- Synopsys Platform Architect
- SoC Performance Modeling
- Emulation Platform
- PCIe
- UCIe
- DDR/CPU/GPU/Interconnect Analysis
- Performance Simulation & Bottleneck Analysis
Added by ChipJobs from Renesas Electronics India's careers page · Posted · 444 days ago · Checked
About the role
Performance-verification engineer in Renesas's SoC architecture group, building performance models with Synopsys Platform Architect and an Emulation Platform to analyze CPU, GPU, DDR, interconnect, PCIe and UCIe subsystems, working with architecture, design, software and verification teams to meet system performance goals.
How we checked this listing
| What we checked | Result | When |
|---|---|---|
| Is this a real posting on the employer's own site? | Opened by hand on Renesas Electronics India's own careers page and entered here. It was live at the time. | 29 Aug 2026 |
| Who put it here? | We found this on Renesas Electronics India's careers page and entered it by hand. The employer has not confirmed it with us. | — |
| Does it have a salary range? | No. The employer does not publish a pay band on this posting. | — |
| Is it still live today? | We have not completed a source re-check since it was entered by hand. It remains marked unchecked. | 29 Aug 2026 |
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Originally posted on the employer's careers page by Renesas Electronics India. ChipJobs links to the employer’s own posting and reproduces no content from LinkedIn, Indeed, Glassdoor or Naukri.
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