Sr Staff Engineer, Digital Design
Renesas Electronics India · Bengaluru · On-site (inferred from location)
- Pay
- Not disclosed
Tell us what this pays
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- Work setup
- On-site (inferred from location)
- Employment
- Full-time (inferred)
- Discipline
- RTL Design
Skills
- Verilog/SystemVerilog RTL
- Clock domain crossing (CDC) analysis
- Low-power digital design
- I2C/SPI/PMBus/SVID protocols
- Silicon debug & bring-up
- Digital lint flows
- State machine & power-sequencer design
Added by ChipJobs from Renesas Electronics India's careers page · Posted · 45 days ago · Checked
About the role
Digital design engineer at Renesas driving the transition from traditional PMICs to Intelligent Power Systems, owning the full design cycle from microarchitecture and RTL through gate-level netlists, silicon debug, and tapeout for mixed-signal power management ICs.
How we checked this listing
| What we checked | Result | When |
|---|---|---|
| Is this a real posting on the employer's own site? | Opened by hand on Renesas Electronics India's own careers page and entered here. It was live at the time. | 29 Aug 2026 |
| Who put it here? | We found this on Renesas Electronics India's careers page and entered it by hand. The employer has not confirmed it with us. | — |
| Does it have a salary range? | No. The employer does not publish a pay band on this posting. | — |
| Is it still live today? | We have not completed a source re-check since it was entered by hand. It remains marked unchecked. | 29 Aug 2026 |
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Originally posted on the employer's careers page by Renesas Electronics India. ChipJobs links to the employer’s own posting and reproduces no content from LinkedIn, Indeed, Glassdoor or Naukri.
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