Staff/ Sr Staff Engineer, Physical Design
Renesas Electronics India · Noida · Hybrid (inferred from location)
- Pay
- Not disclosed
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- Work setup
- Hybrid (inferred from location)
- Employment
- Full-time (inferred)
- Discipline
- Physical Design
Skills
- RTL synthesis
- UPF / low-power design
- LEC (logic equivalence checking)
- VCLP sign-off
- Cadence Genus
- Synopsys Fusion Compiler
- Conformal
- TCL scripting
Added by ChipJobs from Renesas Electronics India's careers page · Posted · 175 days ago · Checked
About the role
Physical design (backend) engineer owning RTL synthesis through sign-off for complex SoC designs, including logic equivalence checking (LEC), UPF power-intent development, and VCLP low-power sign-off, working closely with Physical Design, DFT, and Front-End teams.
How we checked this listing
| What we checked | Result | When |
|---|---|---|
| Is this a real posting on the employer's own site? | Opened by hand on Renesas Electronics India's own careers page and entered here. It was live at the time. | 29 Aug 2026 |
| Who put it here? | We found this on Renesas Electronics India's careers page and entered it by hand. The employer has not confirmed it with us. | — |
| Does it have a salary range? | No. The employer does not publish a pay band on this posting. | — |
| Is it still live today? | We have not completed a source re-check since it was entered by hand. It remains marked unchecked. | 29 Aug 2026 |
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Originally posted on the employer's careers page by Renesas Electronics India. ChipJobs links to the employer’s own posting and reproduces no content from LinkedIn, Indeed, Glassdoor or Naukri.
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